The present application claims the benefit of and priority to a provisional patent application entitled “Method and Structure for Reducing Substrate Parasitics in Silicon-On-Insulator Technologies,” U.S. Ser. No. 62/045,778 filed on Sep. 4, 2014. The disclosure in this provisional application is hereby incorporated fully by reference into the present application.
Radio frequency (“RF”) circuits made by fabricating semiconductor devices, such as transistors, on a semiconductor on insulator (“SOI”) wafer typically suffer from several drawbacks, due to losses associated with substrate impedance. For example, unwanted crosstalk between devices or circuit blocks can occur through the substrate. Moreover, in RF switches built in SOI technologies, the parasitic substrate impedance can result in degraded linearity and voltage imbalance across large branches of stacked semiconductor devices.
Some of the effects experienced by the monolithic RF circuits when utilizing SOI wafers can be partially mitigated by using SOI wafers having a high resistivity substrate. For example, RF switches built on a SOI wafer can use a high resistivity substrate under buried oxide and device layers. Typically, the buried oxide layer in contact with the high resistivity substrate contains positive bulk charge. In addition, fixed charge (e.g., positive charge) is also present at the interface of the high resistivity substrate and the buried oxide layer, for example, thermally grown on the high resistivity substrate. Due to the low background doping of the high resistivity substrate, the positive charge can cause an accumulation of mobile charges of opposite polarity (e.g., negative charge) under the buried oxide layer, resulting in the formation of a parasitic conduction layer (PCL) of high mobility carriers in the high resistivity substrate, which can significantly decrease the effective resistivity of the substrate. For example, if 1000 ohm-cm silicon is used to build a high resistivity substrate, the effective resistivity of the substrate is found to be only approximately one fifth of that value (i.e., 200 ohm-cm) based on transmission line measurements over the substrate.
To address the PCL associated with the high resistivity SOI wafer, a conventional approach is to deposit a defect-rich layer on the high resistivity substrate such that the inversion charge is in a region of low mobility. Although this conventional approach can increase the effective substrate resistivity, due to increased manufacturing complexity, it costs significantly more than the standard high resistivity SOI without the defect-rich layer. According to another conventional approach, a damaged region can be formed in the high resistivity substrate as part of an integrated circuit manufacturing flow, where an amorphizing implant (e.g., argon or germanium) having a high density of carriers is introduced to reduce carrier mobility in the high resistivity substrate. However, the damaged region can re-align to the underlying substrate at temperatures far below what is typically required for CMOS manufacturing (e.g., at 550° C.). As a result, the formation of the damaged regions must happen after the formation of the active devices (e.g., after the source/drain anneal in the CMOS or BiCMOS process flow). Also, such a heavy dose of damaging implant must be done outside of the active device regions to avoid damaging the active devices, which seriously compromises the effectiveness of this approach in applications where large devices are required (e.g., low loss RF switches).
Not only does the PCL under an active device region lower the effective substrate impedance, but because the PCL under the active device region is isolated by the surrounding damaged regions, potential swings in the active device region in the device layer can modulate a depletion region depth in the high resistivity substrate. As a consequence, the depletion regions act as a dielectric medium to form one or more voltage-dependent, non-linear capacitors, such as parasitic varactors, in the high resistivity substrate. These parasitic varactors can contribute to the non-linearity in signals propagating through the device layer, for example, through the source and drain regions of RF switches (e.g., field effect transistors).
Thus, there is a need in the art for a semiconductor on insulator (SOI) structure having improved electrical signal isolation and linearity.